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Information × Registration Number 0126U000233, R & D request Title Designing components of arithmetic logic units on FPGA Head Hryha Volodymyr M., Кандидат технічних наук Registration Date 15-01-2026 Organization Vasyl Stefanyk Carpathian National University popup.description1 The aim of the project is to develop circuit structures and architectures of arithmetic-logic units of modern processors on a modern element base based on programmable logic integrated circuits (FPGA). popup.nrat_date 2026-01-15 Close