Search academic texts

Information × Registration Number 0211U008953, 0109U001604 , R & D reports Title To develop the architecture of the microprocessor with reduction parallelism of organization of the computing process oriented to the tasks of handle popup.stage_title Head Palagin Aleksandr Vasilovich, Registration Date 02-12-2011 Organization V.M.Glushkov Institute of Cybernetics of NASU popup.description2 The fundamentals of algebra for machine control tasks, formulated the concept of the algebraization of the system command, architecture with reduction parallelism of organizing computational processes in a computer. New methods of designing microprocessors architectures, their virtualization engines the synthesis system commands, and the organization of the computational process. Designed functional circuits of the processor, place layout and verification of individual nodes in the system of automatic design firm Xilinx, synthesized instruction set and designed internal language. Product Description popup.authors Безвербний І.А. Візор Я.Є. Семотюк В.М. Семотюк М.В.. popup.nrat_date 2020-04-02 Close