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Information × Registration Number 0313U005221, 0113U005525 , R & D reports Title 3. Designing of an experimental core of the problem- oriented processor for solving the problem of control for orientation of small spacecraft. popup.stage_title Розробка експериментального ядра проблемно-орієнтованого процесора для розв'язання задач управління орієнтацією малих космічних апаратів Head Palagin Alexander Vasiliyevich, Registration Date 28-11-2013 Organization V.M.Glushkov Institute of Cubernetics of NASU popup.description2 Designed of an experimental core of the problem- oriented processor for the implementation of algorithms of estimation and control in the format of floating point (single and double precision) with using CAD Xilinx ISE, and are implemented the simulation for the processor with using of ModelSim. Designed processor, because of the chip FPGA, efficient are used the reconfigurability principle, which allows easy reprogramming of the FPGA crystal sets it for the effective implementation of a given algorithm, what determines its structural flexibility. Reconfiguration of the structure is carried out by recording the configuration file into FPGA. Product Description popup.authors Лісовий Олександр Миколайович Опанасенко Володимир Миколайович Семотюк Мирослав Васильович popup.nrat_date 2020-04-02 Close