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Information × Registration Number 2111U000450, Article popup.category Стаття Title popup.author popup.publication 01-01-2011 popup.source_user Сумський державний університет popup.source http://essuir.sumdu.edu.ua/handle/123456789/22994 popup.publisher Видавництво СумДУ Description In order to achieve both driver and display capability for a number of display devices, TFT has attracted attention, model calculations are therefore presented for the grain boundary barrier height, in a polysilicon TFT considering the charge neutrality between the intrinsic free carriers and the grain boundary trap states. The formation of the potential barrier at a grain boundary is considered due to the trapping of carriers at the localized grain boundary trap states. The trapped charges, influenced by the gate bias voltage and the trapping states density, in turn, have been taken to deplete free carriers near the grain boundary in a device such as polysilicon TFT. The present predictions reveal that the barrier height diversely depends on the gate source voltage (VGS) of a TFT along with other crystal parameter. Finally to obtain the transconductance, the contributions of transverse and longitudinal grain boundary resistances are incorporated in the I-V characteristics of a TFT. For all values of grain size, the transconductance of the device is seen to increase initially with the gate voltage (VGS) which finally appears to be saturated. The dependence of the transconductance on grain size and drain voltage has been thoroughly explored. Good agreement with experimental results is achieved. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/22994 popup.nrat_date 2025-03-24 Close