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Information × Registration Number 2113U000701, Article popup.category Стаття Title popup.author popup.publication 01-01-2013 popup.source_user Сумський державний університет popup.source http://essuir.sumdu.edu.ua/handle/123456789/35651 popup.publisher Sumy State University Description The urge of inventing a new low power consuming device for the post CMOS future technology has drawn the attention of the researchers on Single Electron Transistor [SET]. The two main virtues, ultra low power consumption [1] and ultra small dimension of SET [12, 13] have stimulated the researchers to consider it as a possible alternative. In our past paper [1] we have designed and simulated some basic gates. In this paper we have designed and simulated hybrid SET-CMOS based counter circuits, shift register to show that the hybrid SET-MOS based circuits consumes the lesser power than MOS based circuits. All the simulation were done and verified in Tanner environment using the MIB model for SET and the BSIM4.6.1 model for MOSFET. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/35651 popup.nrat_date 2025-03-24 Close