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Information × Registration Number 2117U000781, Article popup.category Стаття Title popup.author popup.publication 01-01-2017 popup.source_user Сумський державний університет popup.source http://essuir.sumdu.edu.ua/handle/123456789/65996 popup.publisher Sumy State University Description Design consideration of a fully depleted SOI (Silicon-On-Insulator) MOSFET device by three dimensional mathematical modeling is presented in this paper. To the best of our knowledge, when our device is fabricated in nanometer regime, the threshold voltage changes due to various effects. Back gate voltage plays a significant role on the controlling of threshold voltage. Separation of variable is used to solve the Poisson’s three dimensional equation, analytically with suitable boundary conditions for the threshold voltage of double gate SOI MOSFET with the influence of biasing with back gate. In this work, changes in threshold voltage has been calculated and demonstrated that how short channel effects and DIBL can be suppressed with application of Back Gate bias voltage. popup.nrat_date 2025-03-24 Close