Registration Number
0211U013231,
0109U002268
, R & D reports
Title
Arhitecture paradigm and methods of network processor structural design for data packet intellectual processing.
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Head
Simonenko Valeriy Pavlovich,
Registration Date
11-01-2012
Organization
The informatics and computer science faculty the National Technical University of Ukraine "KPI"
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A set of methods for pipelined computer system synthesis is developed. The methods are based on mapping the spaced synchronous dataflow graphs (SSDFG) into the system structure and its schedule. The input data of the methods are initial SSDFG, given period of the algorithm implementation, and optimization criterium. The developed methods provide minimizing the clock period as well as processor unit, register, multiplexor number, interprocessor communications, memory volume, energy consumption minimizations. A set of methods for synthesis of the pipelined computer systems for the field programable gate array (FPGA) is developed. It includes method based on the VHDL language, method of mapping the iterative algorithms with the control operators. A set of intelectual property cores (IP cores) for the configurable network processor building is developed. It contains the media acces controller core, Reed-Solomon decoder, GZIP file decompressor. i8051 microcontroller core is developed which has increased speed up to 100 mln. instructions per second. An experimental network processor based on Xilinx XCV-4SX35 FPGA was designed and probed.
Product Description
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Лепеха Володимир Львович
Сергієнко Анатолій Михайлович
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2020-04-02
