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Information × Registration Number 0315U005013, 0114U005074 , R & D reports Title 3. Development the Cores of the Controller of Bus PCI Express x8 Lane and controller of memory access based on CAD PLD popup.stage_title Розробка ядер контролеру шини PCI Express x8 Lane та контролеру доступу до пам'яті на базі САПР ПЛІС Head Palagin Alexander Vasiliyevich, Registration Date 26-01-2015 Organization V.M.Glushkov Institute of Cubernetics of NASU popup.description2 The experimental cores of the controller direct memory access and the controller Bus PCI Express x8 Lane for a connection the problem-oriented processor to basic computer by means PLD CAD were developed. They ensure the functioning of the processor for the implementation of the existing algorithms for solving problems controlling the orientation of the spacecraft and also the simplicity and portability of their reconfiguration. Product Description popup.authors Лісовий Олександр Миколайович Опанасенко Володимир Миколайович Семотюк Мирослав Васильович popup.nrat_date 2020-04-02 Close