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Information × Registration Number 2122U006284, Article popup.category Препринт Title Optimizing RISC-V core for machine learning workloads (AI translated) popup.author Kuchynskyy VolodymyrKuchynskyy Volodymyr popup.publication 01-01-2022 popup.source_user Український католицький університет popup.source https://hdl.handle.net/20.500.14570/4393 popup.publisher Description Machine learning has become widely used in many different applications. Specifically, machine learning models on embedded edge systems have been gaining popularity. Due to the high resource requirements of machine learning workloads and highly-constrained embedded systems, the idea of using custom hardware accelerators has become viable. Open-source CPU architectures such as RISC-V could be used for such purposes. Additionally, Field-Programmable Gate Arrays (FPGAs) offer a useful platform for running and prototyping custom hardware. In this thesis, we review the current state of machine learning acceleration hardware, optimize a MobileNetV1 model and describe a design process for prototyping hardware acceleration using CFU playground framework. popup.nrat_date 2025-11-05 Close