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Information × Registration Number 0216U003107, 0113U000070 , R & D reports Title Develop and implement a physical simulation on FPGA Hardware support for parallel computing and multi-level management processes popup.stage_title Head Yakovlev Yuriy Sergeevich, Registration Date 14-01-2016 Organization V.M.Glushkov Institute of Cubernetics of NASU popup.description2 Developed in CAD FPGA basis set of 10 units and blocks of a computer system, which is implemented by solving the problem of parallelism due to the instrumental support. Perform verification, synthesis and simulation concepts of nodes and the proposed set of units used for paralleling. Thus, basically, we used CAD packages f. Xilinx, p. Atmel and others. The use of this set will reduce the time parallelization and solving the problem by an average of 2 to 5-times and also reduce the resources and reduce energy consumption of computer equipment. The proposed set of different multi-purpose, and therefore it is possible to create temporary virtual information spaces and subsystems and flexibly reconfigure them for the optimal solution of typical problems in various spheres of human activity. For the validation of technical solutions designed and developed virtually universal stand test, the PCB is placed chip FPGAs, which implement one of the blocks set by running with the full cycle of its physical model. The end result of this project are the physical model circuit components and units made on the FPGA and displayed in the form of appropriate reports on the results of the synthesis, simulation and other procedures used CAD FPGA presented in the selected language (for example, high-level language VHDL or Verilog). Product Description popup.authors Єлісєєва О.В. Єресько В.В. Бурак В.В. Вишинський В.А. Дем'янцева Н.І. Долієвський Г.В. Комухаев Е.Г. Кононенко О.Ю. Курзанцева Л.І. Нестеренко М.В. Перегонцев О.С. Самолюк Т.А. Сліпець А.В. Сосненко К.П. Столбченко М.І. Тимашов О.О. Чічірін Є.М. Яковлєв Ю.С. popup.nrat_date 2020-04-02 Close